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Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
FEATURES
* 8 differential 3.3V LVPECL / ECL outputs * 2 selectable differential LVPECL input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >2GHz (typical) * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLKx input * Output skew: 50ps (maximum) * Part-to-part skew: 200ps (maximum) * Propagation delay: 900ps (maximum) * LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3V to -3.8V * -40C to 85C ambient operating temperature * Pin compatible with MC100LVE310
GENERAL DESCRIPTION
The ICS853310 is a low skew, high performance 1-to-8 Differential-to-3.3V LVPECL/ECL HiPerClockSTM Fa n o u t B u f fe r a n d a m e m b e r o f t h e HiPerClockS TM family of High Performance Clock Solutions from ICS. The PCLKx, nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL differential input levels. The ICS853310 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853310 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
PCLK0 nPCLK0
PCLK1 nPCLK1 0 1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2
VCCO nQ0 nQ1 nQ2 Q0 Q1 Q2
25 24 23 22 21 20 19 VEE CLK_SEL PCLK0 VCC nPCLK0 VBB 26 27 28 1 2 3 4 5
nPCLK1
18 17 16
Q3 nQ3 Q4 VCCO nQ4 Q5 nQ5
CLK_SEL
Q3 nQ3 Q4 nQ4
ICS853310
15 14 13 12
V BB
Q5 nQ5 Q6 nQ6 Q7 nQ7
PCLK1
6
nc
7
nQ7
8
VCCO
9 10 11
Q7 nQ6 Q6
REV. A JUNE 18, 2004
28-Lead PLCC 11.6mm x 11.4mm x 4.1mm package body V Package Top View
853310AV
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Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7, 9 8, 15, 22 10, 11 12, 13 14, 16 17, 18 19, 20 21, 23 24, 25 26 27 28 Name VCC nPCLK0 VBB PCLK1 nPCLK1 nc nQ7, Q7 VCCO nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 VEE CLK_SEL PCLK0 Power Input Output Input Input Unused Output Power Output Output Output Output Output Output Output Power Input Input Core supply pin. Pullup/ Inver ting differential LVPECL clock input. VCC/2. Pulldown Bias voltage. Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential LVPECL clock input. VCC/2. Pulldown No connect. Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Clock Select input. When HIGH, selects PCLK1, nPCLK1 inputs. When Pulldown LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input.
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REV. A JUNE 18, 2004
Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (LVECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to V + 0.5 V
CC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (LVECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG Wave Solder, TSOL
0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C 265C
cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Temperature Range, TA -40C to +85C
TABLE 2A. LVPECL POWER SUPPLY DC CHARACTERISTICS, VCC = 3V TO 3.8V; VEE = 0V
Symbol VCC VCCO I EE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.0 3.0 Typical 3.3 3.3 Maximum 3.8 3.8 70 Units V V mA
Table 2B. LVPECL DC Characteristics, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage (Single-Ended) Input Low Voltage (Single-Ended) Output Voltage Reference; NOTE 2 -40C Min 2.175 1.405 2.075 1.43 1.86 Typ 2.275 1.545 Max 2.38 1.68 2.36 1.765 1.98 Min 2.225 1.425 2.075 1.43 1.86 25C Typ 2.295 1.52 Max 2.37 1.615 2.36 1.765 1.98 Min 2.295 1.44 2.075 1.43 1.86 1.765 1.98 85C Typ 2.22 1.535 Max 2.365 1.63 Units V V V V mV
Peak-to-Peak Input Voltage 500 1000 500 1000 500 1000 mV Input High Voltage VCMR 1.8 2.9 1.8 2.9 1.8 2.9 V Common Mode Range; NOTE 3 PCLK0, PCLK1 Input High IIH 150 150 150 A nPCLK0, nPCLK1 Current CLK_SEL PCLK0, PCLK1, Input Low nPCLK0, nPCLK1 IIL -150 -150 -150 A Current CLK_SEL NOTE 1: Input and output parameters vary 1:1 with VCC. VEE can vary 0.3V. Please refer to Parameter Measurement Information, "Output Load AC Test Circuit". NOTE 2: Outputs terminated with 50 to VCCO - 2V. NOTE 3: VCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1V and greater than or equal to VPP(min).
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REV. A JUNE 18, 2004
Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Test Conditions Minimum -3.0 Typical -3.3 Maximum -3.8 70 Units V mA
TABLE 2C. LVECL POWER SUPPLY DC CHARACTERISTICS, VCC = 0V; VEE = -3.3V 0.3V
Symbol VEE IEE Parameter Supply Voltage Power Supply Current
Table 2D. ECL DC Characteristics, VCC = 0V; VEE = -3.3V 0.3V
Symbol VOH VOL VIH VIL Parameter Output High Voltage Output Low Voltage Input High Voltage (Single-Ended) -40C Min -1.125 -1.895 -1.225 Typ -1.025 -1.755 Max -0.92 -1.62 -0.94 Min -1.075 -1.875 -1.225 25C Typ -1.005 -1.78 Max -0.93 -1.685 -0.94 Min -1.005 -1.86 -1.225 85C Typ -1.08 -1.765 Max -0.935 -1.67 Units V V V
Input Low Voltage (Single-Ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V Output Voltage Reference; -1.44 -1.32 -1.44 -1.32 -1.44 -1.32 mV V BB NOTE 1 Peak-to-Peak Input Voltage 500 1000 500 1000 500 1000 mV V PP Input High Voltage 1.5 -0.4 1.5 -0.4 1 .5 -0.4 V VCMR Common Mode Range; NOTE 2 PCLK0, PCLK1, Input High IIH nPCLK0, nPCLK1 150 150 150 A Current CLK_SEL PCLK0, PCLK1, Input Low nPCLK0, nPCLK1 IIL -150 -150 -150 A Current CLK_SEL NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: VCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1V and greater than or equal to VPP(min).
TABLE 3. AC CHARACTERISTICS, VCC = 3.3V; VEE = 0V OR VCC = 0V; VEE = -3.3V
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% 100 700 -40C Min Typ >2 900 75 250 400 100 750 Max Min 25C Typ >2 950 50 200 400 100 775 Max Min 85C Typ >2 975 50 200 400 Max Units GHz ps ps ps ps
t PD tsk(o) tsk(pp)
tR/tF
VEE can ver y 0.3V. All parameters measured at 1.2GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JUNE 18, 2004
Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
V CC
LVPECL
nQx
VEE
nPCLK0, nPCLK1
V
PCLK0, PCLK1
PP
Cross Points
V
CMR
-1.3V 0.3V
V EE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx
nQx PART 1 Qx nQy
nQy Qy
PART 2 Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nPCLK0, nPCLK1 PCLK0, PCLK1
nQ0:nQ7 Q0:Q7
tPD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
PROPAGATION DELAY
853310AV
OUTPUT RISE/FALL TIME
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REV. A JUNE 18, 2004
Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 1A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to
the negative input. The C1 capacitor should be located as close as possible to the input pin.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference
voltage level VBB generated from the device is connected to the negative input.
VCC(or VDD)
CLK_IN
PCLK VBB nPCLK
FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
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Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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REV. A JUNE 18, 2004
Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
R1 50
R2 50
PCLK
3.3V Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3 125
R4 125
PCLK
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
C1
PCLK
Zo = 50 Ohm
C2
VBB nPCLK
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
PC L K/n PC LK
R5 100 - 200
R6 100 - 200
R1 50
R2 50
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK R4 120
3.3V
Zo = 50 Ohm
LVDS
R5 100
Zo = 50 Ohm
HiPerClockS PCLK/nPCLK
C1
PCLK
C2
VBB nPCLK
PC L K /n PC L K
R1 120
R2 120
R1 1K
R2 1K
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 3F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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REV. A JUNE 18, 2004
Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
capacitors should be physically located near the power pin. For ICS853310, the unused outputs can be left floating.
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of the ICS853310. In this example, the PCLK0/nPCLK0 input is selected. The decoupling
Zo = 50
+
Zo = 50
-
3.3V
R2 50
R1 50
VCC
U1
Zo = 50 Ohm
VCC
Zo = 50 Ohm
26 27 28 1 2 3 4
Q0 nQ0 Q1 VCCO nQ1 Q2 nQ2
25 24 23 22 21 20 19
C6 (Option) 0.1u
R3 50
LVPECL Driv er
R9 50
C5 (Option) 0.1u
R10 50
R3 1K
ICS853310
R11 50
Zo = 50
+
VCC=3.3V
Zo = 50
5 6 7 8 9 10 11
nPCLK1 nc nQ7 VCCO Q7 nQ6 Q6
VEE CLK_SEL PCLK0 VCC nPCLK0 VBB PCLK1
Q3 nQ3 Q4 VCCO nQ4 Q5 nQ5
18 17 16 15 14 13 12
-
(U1-8)
VCC
(U1-15)
(U1-22)
(U1-1)
R8 50
R7 50
C1 0.1uF
C2 0.1uF
C3 0.1uF
C4 0.1uF
C7 (Option) 0.1u
R13 50
FIGURE 4A. ICS853310 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC EXAMPLE
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ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
pin as possible. It is preferable to locate the bypass capacitor on the same side as the IC. Figure 4B shows suggested capacitor placement. Placing the bypass capacitor on the same side as the IC allows the capacitor to have direct contact with the IC power pin. This can avoid any vias between the bypass capacitor and the IC power pins. The vias should be placed at the Power/Ground pads.There should be a minimum of one via per pin. Increasing the number of vias from the Power/Ground pads to Power/Ground planes can improve the conductivity.
POWER, GROUND AND BYPASS CAPACITOR
This section provides a layout guide related to power, ground and placement of bypass capacitors for a high-speed digital IC. This layout guide is a general recommendation. The actual board design will depend on the component types being used, the board density and cost constraints. This description assumes that the board has clean power and ground planes. The goal is to minimize the ESR between the clean power/ground plane and the IC power/ground pin. A low ESR bypass capacitor should be used on each power pin. The value of bypass capacitors ranges from 0.01uF to 0.1uF. The bypass capacitors should be located as close to the power
GND
IC
FIGURE 4B. RECOMMENDED LAYOUT
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C
Power Pad
Power pin
GND Pad
GND Pin
Via
OF
BYPASS CAPACITOR PLACEMENT
REV. A JUNE 18, 2004
Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853310. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853310 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 70mA = 266mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 8 * 30.94mW = 247.5mW
Total Power_MAX (3.8V, with all outputs switching) = 266mW + 247.5mW = 513.5mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 4 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.514W * 31.1C/W = 101C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 4. THERMAL RESISTANCE JA
FOR
28-PIN PLCC, FORCED CONVECTION
by Velocity (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.8C/W
200
31.1C/W
500
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT RL 50 VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V
OH_MAX
=V
CCO_MAX
- 0.935V
(VCCO_MAX - VOH_MAX) = 0.935V * For logic low, VOUT = V (V
CCO_MAX
OL_MAX
=V
CCO_MAX
- 1.67V
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO _MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. A JUNE 18, 2004
Integrated Circuit Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 5.
JAVS. AIR FLOW TABLE FOR 28 LEAD PLCC
by Velocity (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.8C/W
200
31.1C/W
500
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853310 is: 462
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ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
28 LEAD PLCC
PACKAGE OUTLINE - V SUFFIX
FOR
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 4.19 2.29 1.57 0.33 0.19 12.32 11.43 4.85 12.32 11.43 4.85 MINIMUM 28 4.57 3.05 2.11 0.53 0.32 12.57 11.58 5.56 12.57 11.58 5.56 MAXIMUM
Reference Document: JEDEC Publication 95, MS-018
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ICS853310
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Marking ICS853310AV ICS853310AV Package 28 Lead PLCC 28 Lead PLCC on Tape and Reel Count 38 per Tube 500 Temperature -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS853310AV ICS853310AVT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853310AV
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